This invention relates to a method and an apparatus for cache lock control which are usable in an information processing system including a cache memory.
In general, a cache memory is connected between a CPU and a main memory in an information processing system. The cache memory is a small and fast storage buffer which temporarily stores data used by the CPU. When data required by the CPU is present in the cache memory, the CPU uses the data in the cache memory and therefore it is unnecessary for the CPU to execute access to the main memory. As the CPU is allowed to more frequently use the cache memory, an average time spent in access to data can be shorter.
Since the capacity of the cache memory is smaller than the capacity of the main memory, the cache memory can store a limited quantity of data which equals only a part of all the data in the main memory. Accordingly, in the cache memory, there is a possibility that data used by the CPU at a high frequency is replaced by data used by the CPU at a low frequency. From the standpoint of fast access to data, it is desirable to inhibit the replacement of data used at a high frequency by data used at a low frequency.
A cache lock arrangement has been developed to inhibit the updating of data in the cache memory, which is used by the CPU at a high frequency or which should be quickly fed to the CPU. Cache memories such as he model CY7C604/CY7C605 produced by Cypress Semiconductor, use such a cache lock arrangement in an information processing system as disclosed in "SPARC RISC USER'S GUIDE", February 1990.
In a prior art cache lock arrangement, the updating of data in a cache memory can be controllably inhibited, that is, the cache memory can be controllably locked. When data which should be quickly fed to a CPU is preset in the cache memory or when data used by the CPU at a high frequency is present in the cache memory, the cache memory is generally locked.
Data which should be quickly fed to the CPU, and data used by the CPU at a high frequency are now referred to as more-required data. Other data, for example, data used by the CPU at a low frequency, is now referred to as less required data. In the prior art cache lock arrangement, the cache memory tends to be locked even when only a part of data in the cache memory agrees with more-required data and the other data in the cache memory corresponds to less-required data. In this case, the less-required data continues to be present in the cache memory. The continuous presence of the less-required data in the cache memory lowers an average speed of access to data. Furthermore, after the cache memory is locked, it is generally difficult to replace such less-required data by more-required data.